Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
A schematic representation of a typical electronic inverter 100 is shown in FIG. 1. In such inverters, an incoming signal 110 having a specific frequency and form is fed into input 115 of the inverter 100. Input 115 is coupled to the gates of pMOS transistor 120 and nMOS transistor 125, as shown in FIG. 1. The pMOS 120 and nMOS 125 transistors are biased across the VDD drain 130 and VSS source 135 using a static or dynamic voltage based on a reference voltage applied at VDD drain 130. VSS source 135 can be tied to ground in some implementations. The inverted signal 160 is then output on terminal 140 that is coupled to the drain lead of pMOS transistor 120 and the drain lead of the nMOS transistor 125. The output is loaded by capacitor 150 coupled to the terminal 140 and the drain lead of the nMOS transistor 125.
The speed of electronic inverters, like inverter 100, that use MOS transistors, is dependent on the transit frequencies of the pMOS and nMOS transistors 120 and 125. The transit frequency of a MOS transistor describes the speed at which the transistor can be operated. The transit frequencies of the pMOS and nMOS transistors 120 and 125 varies with the transconductance, GM, of the pMOS and nMOS transistors 120 and 125. Thus, if the GM of the pMOS and nMOS transistors 120 and 125, and consequently the transit frequencies of the pMOS and nMOS transistors 120 and 125, can be kept substantially constant over temperature and process corner variations, then the transition speed of the inverter will also remain constant, or at least within an acceptable range. When the transition speed of the inverter is constant or within an acceptable range, its contribution to overall phase noise or phase noise variation can be reduced or eliminated.
Maintaining constant transit frequencies in the pMOS and nMOS transistors 120 and 125, requires that the transistors be biased with varying voltages that corresponds to the threshold and mobility variation in the transistors due to the temperature and process corner variations in a given operating condition to maintain constant transconductance across the transistors. For example, in situations with fast-corner signals at relatively low temperature, there is no need for a high VDD 130 for the inverter to function a sufficiently high speeds, because the transfer frequency of the inverter will be high enough to supply a signal to other electronic components with little to no phase noise. However, in slow-corner scenarios at high temperatures, or high PT, the transfer frequency of the inverter may be too slow for high speed applications. To compensate for the relatively low transfer frequency of the inverter components, i.e. the pMOS and the nMOS devices 120 and 125, at higher temperatures, the reference voltage, VDD, can be increased to increase the transconductance, GM, of the transistors, and, consequently, the operational speed of the inverter. Ensuring that the inverter operates at speeds sufficient to keep up with frequency of the incoming signal or waveform, helps to reduce or eliminate phase noise injected into any system or device in which the inverter is used.
One fail safe method of ensuring that the inverter will always operate to transition the incoming signal at sufficiently high speeds with limited, if any, added phase noise, is to operate the inverter with a relatively high VDD. This usually means operating the inverter with a reference voltage, VDD, set for the worst case scenario in which the inverter would be expected to operate, i.e. the highest operating temperature. Unfortunately, this means that more power would be used for supplying the high VDD than is necessary for most conditions which, of course, results in higher power consumption than is necessary for most scenarios. Obviously, unnecessary high power consumption is not a desirable characteristic for most electronic devices.
Assuming linear performance of the transconductance, GM, of the transistors, if an inverter can be biased with a voltage or current in the middle of a transition, then the phase noise and the rate of the transition can also be kept constant. To maintain constant GM in the inverter, the reference voltage applied to VDD can be varied based on simulated operation or measurement of operational parameters in actual use that can be used to adjust the reference voltage to maintain constant transition frequency and phase noise. However, contemporary systems for adjusting the VDD to maintain constant operation of the inverter often time require expensive active systems with computational logic, sensors and calibrated look-up tables.